The invention relates to the general field of integrated circuits with particular reference to photolithography.
It is often the case in current integrated circuit technology that there will be two field effect transistors (FETs) that are situated close to one another but, because they will be used to perform different functions (e.g. one might be part of a logic circuit while the other is part of a memory array) the thicknesses of their gate oxides will not be the same. There are several approaches to manufacturing such dual gate structures. The approach used as part of the present invention is to start with a substrate, such as a silicon wafer 11, as illustrated in FIG. 1, and form shallow isolation trenches 12 in the surface, the intent being to form one FET per inter-trench space.
Accordingly, oxide layer 13 is first formed on the surface following which those portions that are to be used for the thicker oxide devices are protected by photoresist mask 21 (FIG. 2). The next step is to then etch the unprotected portions of oxide layer 13 so as to reduce its thickness there. An important aspect of the process is that the step that follows, which is the routine removal of photoresist mask 21, is performed using a wet strip process instead of the more usual plasma dry ashing process. This is to prevent damage to the dual gate oxide by the high energy plasma that is part of the ashing process.
The intent of the of the above-described process is to form the structure shown in FIG. 3. Unfortunately, it has been found that there is often an undesirable side effect which we have illustrated schematically in FIG. 4. Shown there is defect 44 that appears at the interface between the two thicknesses of oxide, 23 and 13. 44 is a particle of silicon carbide (SiC) that can form due to unsaturated bonds on the photoresist surface, at the edge of the photoresist pattern, that will react with SiF6 during the wet etch process.
These SiC defects stay on the wafer surface after the wet strip process, and can cause shorts or opens of the poly lines, depending on their size. The present invention discloses a process for ensuring that said SiC defects do not form.
A routine search of the prior art was performed with the following references of interest being found:
A process for forming a dual gate dielectric is described by Fang et al. in U.S. Pat. No. 5,588,035. In U.S. Pat. No. 6,146,795, Huang et al. form two oxide layers of different thicknesses by first forming a single oxide layer all over, removing the oxide from one area, and then performing a second oxidation step all over. The problem to which they provide a solution is how to ensure that there is no residual photoresist left behind prior to initiating the second oxidation step. The process that they disclose is the use of a low power plasma etch done in combination with X-ray spectroscopy (to detect carbon) to ensure that all photoresist is removed while at the same time not damaging the oxide that has been left in place.
It has been an object of the present invention to provide a process for the formation of dual gate devices having different gate oxide thicknesses.
Another object of the invention has been that no defects get formed at the interface between the two different gate oxide thicknesses.
Still another object has been to remove unsaturated chemical bonds from the edge of the photoresist mask that is used in the process.
These objects have been achieved by preceding the HF wet dip (that is used to thin out the oxide) with exposure of the photoresist to a low power plasma that includes some oxygen. This treatment removes unsaturated chemical bonds from the resist surface and prevents the formation of SiC based defects. Such defects could cause polysilicon lines to short or open, depending on their size.